Intel process node

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Intel Rebrands Its Future Process Nodes, Updates Roadmap

Intel has made some major changes and announcements concerning upcoming products and how future improvements to the company’s manufacturing will be communicated. These changes will have a significant impact on how we talk about Intel products going forward.

Decades ago, there was an industry group responsible for defining the characteristics of each new lithography node and an agreed-upon convention for what a new node meant. The actual practice of naming a node in nanometers — 45nm, 32nm, 28nm, and so on — has been divorced from any objective metric for many years now. Today, TSMC, Intel, and Samsung all have different standards for what a given “node” is. TSMC’s 16nm FinFET process retained many of the same dimensions as its 20nm node, but added FinFET. 12nm was then a further refinement of 16nm, but it did not offer the density improvement that the numerical reduction from 20nm to 12nm would imply. These differences between companies are why we have often written that Intel’s 14nm was more comparable to TSMC’s 10nm, and its 10nm more comparable to TSMC’s 7nm.

Intel’s new method for communicating node improvements acknowledges this fact. The company will drop the “nm” from future nodes and refer to them by number alone — Intel 7, Intel 4, and so on down the line. The “A” stands for “angstrom”, the unit of measurement below nanometer. One angstrom = 100 picometers, while one nanometer = 1000 picometers.

Previous nodes will still be referred to by their original nomenclature. Tiger Lake is still considered to be built on Intel’s 10nm process. When Alder Lake launches, however, its “Enhanced SuperFin” won’t be labeled as 10nm++ or +++ or what have you — it’ll be built on Intel 7. Intel 7nm, when it arrives, will be known as Intel 4. It is not clear whether Intel 3 represents a refined 7nm node or 5nm, but refined 7nm seems more likely. Intel’s 7nm is expected to sample in 2022 and ship for volume in 2023, and the “breakthrough” of Intel 20A is expected in H1 2024. This may suggest a two-tier approach where Intel 3 is a refined and polished version of Intel 4, but not a new node. Intel might also introduce 20A for mobile first while holding desktop chips back on the older node, as it’s done since Broadwell debuted in 2014.

Renaming the nodes to a dimensionless number is fine by us. Metrics like “7nm” are essentially dimensionless already. Appending “nm” to the back of the number as if there’s a relationship between the node name and the metric is confusing and encourages people to believe such a relationship exists.

According to Intel, its new node names are based on relative improvements to performance-per-watt, not raw performance. At present, node names are not clearly anchored to any single metric of improvement (performance, power, or area). New nodes have always been occasions for foundries to tout their manufacturing prowess, but the specific improvements of a node transition are particular to itself. The large gap between 28nm and 20nm would seem to imply that the latter would be a major node, but relatively few companies used it. TSMC’s 16nm FinFET (which used the same BEOL as 20nm) was the major node. AMD’s shift from 32nm SOI to 28nm planar silicon at GF did not have a significant net impact on power consumption, even though the node number fell by 4. TSMC’s 5nm offers modest performance and power consumption advances over its 7nm node, but it’s up to 1.8x more dense, compared to power and performance gains in the 1.15x – 1.2x range. I’ve written in the past that new nodes are defined by whatever chum bucket of technology engineers can dump in to make things work better after node shrinks make everything worse, and this will continue to be true.

This slide also reiterates that Intel will introduce EUV at 7nm 4 and extend its usage at 3. At 20A, Intel will introduce ribbonFETs. These are its version of the nanowires and nanosheet technology currently being researched at TSMC and Samsung. Intel 3 will be the company’s last iteration of FinFET, and Intel wants to be in a position of “unquestioned leadership” by 2025. Intel 4 will be a full node die shrink from Intel 7.

PowerVia is Intel’s new technology for power delivery. Instead of running interconnects on top of the transistor stack, all such circuitry will move to the bottom. According to Intel, this allows the top of the chip to be used for signal routing, eliminates voltage droop (with a corresponding improvement in power efficiency), and would allow the company to use either denser signal routing in total or faster wire speeds. Wire speed is a major source of delay in modern chip designs, so improvements here are very useful.

Beyond PowerVias, Intel is working on two new 3D interconnect technologies: Foveros Omni and Foveros Direct. Foveros Omni features copper columns to move power to the top die of the Foveros stack, minimizing the TSV penalty for this kind of bonding. Foveros Omni will also enable Intel to combine different base nodes built on different manufacturing processes together and offers 25-micron solder bumps. Foveros Direct allows for direct copper-copper bonds with 10-micron bumps, boosting overall density. Intel has not revealed if EMIB, its 2.5D bridge interconnect, will continue to evolve.

Intel will introduce 12 layers of EUV at Intel 4 and an unknown for Intel 3 and Intel 20A. Intel has not ordered as many EUV machines as some of its competitors, but it expects to deploy high-NA EUV machines in the future. High-NA EUV is an alternative to multi-patterned EUV, and it’s possible Intel intends to make larger EUV purchases when high-NA machines are finally available.

Intel Doubles Down on Manufacturing Prowess

Intel is emphasizing its historic manufacturing chops with these announcements. It’s similar to what the company did back in 2018 for its Tech Day, with the caveat that late 2021/early 2022 will be the first time we see some of the technologies Intel announced then, like Foveros, in shipping hardware.

Intel’s implicit argument to potential foundry customers and end-users alike is that its 10nm troubles represented a deviation from decades of excellent execution, not a new normal for the company. Over the last 30 years, Intel has led the semiconductor industry for much longer than it has lagged it. Appointing a longtime Intel insider like Pat Gelsinger was part of Intel’s strategy to paint itself as returning to its roots.

But Intel isn’t just aiming for a return to its glory days. The company told us that advanced nodes, explicitly including Intel 3 and Intel 20A, will be offered to its foundry customers. The implication is that technologies like Foveros, Foveros Omni, Foveros Direct, and PowerVias will be as well. Intel wants its customers to associate it with manufacturing excellence, whether the silicon inside a given device is x86-based or not. In order to make that happen, it’ll need to offer competitive solutions against rival TSMC.

Last month, I wrote a deep dive into the question of whether comparisons between so-called “CISC” and “RISC” CPUs are an effective way to compare modern microprocessors. Back in the mid-1990s to early 2000s, Intel’s superior manufacturing was key to its long-term success and x86’s eventual takeover of the CPU market. TSMC and Samsung are much more capable than any RISC CPU manufacturer was in that era, while Intel is in a weaker relative position, but the company’s launch roadmap is aggressive.

As scaling becomes more difficult, the absolute contribution of lithography to each node’s performance, power, and area improvements has already begun to drop. Intel’s decision to emphasize alternative interconnect technologies alongside an eventual shift to ribbonFETs acknowledges this trend. We don’t know how Foveros, Foveros Omni, or Foveros Direct will compare with offerings from TSMC, but any advantages Intel can wring from its new interconnect methods can be used to lower overall x86 power consumption, improve performance, or both.

Oh, one last tidbit: Intel’s Meteor Lake taped in this quarter. Tape-in means the various design groups contributing IP blocks to Meteor Lake have submitted their work to the final product database. This is distinct from tape-out, which refers to sending a completed design to the factory for manufacturing. Meteor Lake is expected to launch in 2023, so we’re still a few years from commercial volume.

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Intel Process Roadmap Through 2025: Renamed Process Nodes, Angstrom Era Begins

Intel CEO Pat Gelsinger whipped the covers off the company's new process and packaging roadmap that now stretches out to 2025, outlining an annual cadence of the company's future process nodes spanning from standard nanometer-scale tech down to incredibly small angstrom-class transistors. Intel also teased the first details of its angstrom-class (the next measurement below nanometer) technology, like RibbonFET, its first new transistor design since FinFET arrived a decade ago, and PowerVia, a new backside power delivery technique that sandwiches the transistors between layers of wiring. Intel will also change its process node naming scheme again, this time to match the naming used by external foundries like TSMC. That re-branding begins with Intel's 10nm Enhanced SuperFin, which will now be renamed to 'Intel 7.'

Intel says its process tech will match the current industry leader, TSMC, by 2024, and that it will retake 'process performance leadership' by 2025, helped along by being the first company to receive a next-gen High NA EUV machine from ASML for its next-gen chips. Intel also shared details of its future Foveros Omni and Direct technologies during its 'Intel Accelerated' webcast and announced that its Sapphire Rapids chips would be the "first dual-reticle-sized device" in the industry.

Intel's fledging foundry services business also notched two big wins, with AWS announcing that it will use Intel's packaging services while Qualcomm announced that it will explore using Intel's 20A process for future chip designs. Let's dive in. 

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Intel Renames 10nm to 7nm

Before we get to the roadmaps, in a necessary move that will likely draw criticism, Intel is renaming its process nodes to align with the current naming conventions used by the third-party foundries like TSMC and Samsung.

This new policy begins with what was known as the 10nm Enhanced SuperFin process that is set to debut with the Alder Lake processors. Intel announced this process node long ago, and it is already in volume production.

Intel is rebranding the next 10nm node to 'Intel 7' and discarding the 'nanometer' nomenclature, so we won't see the traditional 'nm' suffix attached to the company's process nodes anymore. Instead, Intel will name its nodes based on performance, power, and area advances. As a result, all of Intel's successive node names will be adjusted as well, with Intel's 7nm becoming 'Intel 4,' and so on.

Intel's shift in node naming comes as it builds out its own Intel Foundry Services (IFS) business, which will see it make chips for other companies as part of its IDM 2.0 initiative. Intel's IFS will compete directly with TSMC and Samsung, and given that the node naming convention is already broken, aligning with the rest of the industry makes plenty of sense.

However, changing the 10nm Enhanced SuperFin naming while the 'vanilla' 10nm SuperFin is already shipping definitely isn't as ideal as waiting for an entirely new node to make the change — this approach is unquestionably more confusing. In either case, Intel will eventually have to take criticism for making a change to its nomenclature at some point, and it has chosen to do so with its next line of chips. We'll come back to expand on this topic a bit later in the article.

Intel Process Roadmap 2021 - 2025

Intel's roadmap below starts with the 10nm SuperFin that currently ships in some of its products, like its Tiger Lake processors. However, as noted above, 'Intel 7' is the same 10nm Enhanced SuperFin process that Intel has already announced will power its Alder Lake and Sapphire Rapids chips — it just has a new name.

Similarly, Intel's 7nm, which it recently announced will be delayed, is now branded as 'Intel 4.' The remaining two entries on the roadmap, 'Intel 3' and 'Intel 20A' represent what intel previously branded as 7+ and 5nm, respectively. 

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Intel says that 'Intel 7,' the process formerly known as '10nm Enhanced SuperFin,' will ship this year for client (Alder Lake), and for the data center (Sapphire Rapids) in the first quarter of 2022. Intel says that 'Intel 7' delivers 10% to 15% more performance-per-watt than its predecessor, 10nm SuperFin.

As normal, that can translate to either higher peak performance (at the expense of efficiency) or increased efficiency (at the expense of performance), but you can't have both simultaneously. It's noteworthy that higher performance doesn't scale linearly due to the increased power required at the upper end of the voltage/frequency curve, so Intel 7 likely won't be 15% faster than 10nm SuperFin.

Moving on to newer climes, Intel 4 (previously known as 7nm) comes to market in products in the first half of 2023, though it will "be ready for production" in the second half of 2022. Intel says this node provides a 20% performance-per-watt gain over its predecessor (the same rules above apply) and represents the company's full embrace of EUV technology. That's an important step forward — Intel's laggardly adoption of EUV fabrication is thought to be a major contributing factor to its 10nm delays.

Chips based on the Intel 4 process will debut in 2023, with client Meteor Lake processors coming in the first half and Granite Rapids server products following. That timeline still leaves Intel's competitors, like TSMC and Samsung, with a process node advantage in the 2023 time frame. TSMC projects it will be in full production of its 3nm node in 2023, explaining Intel's continued need to outsource some products. Intel plans to leverage its packaging technology and disaggregated design philosophy to integrate externally-produced TSMC chips into its own products to help sidestep the delay. 

Intel 3, previously branded as 7+, will bring an 18% performance-per-watt gain over Intel 4 when it shows up in products in the second half of 2023. 'Intel 3' is an incredibly fast follow to 'Intel 4' that launches earlier the same year, due to the previously mentioned delays. Still, Intel has confirmed that, based on its early modeling and test chip data, it represents "a higher level of improvement than a standard full node for Intel — or indeed for other vendors."

Intel plans to begin an entirely new era in the first half of 2024: The angstrom era. These chips represent the point where some physical features can no longer be accurately measured in nanometers, or billionths of a meter. Instead, these features will now be measured in angstroms, or one ten-billionth of a meter. The first angstrom-class process from Intel will come as 20A (A is for angstrom), which brings RibbonFET, Intel's first gate-all-around (GAA) transistor, and PowerVia, a novel approach to delivering power to incredibly small transistors.

Intel Angstroms, RibbonFET and PowerVia

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RibbonFET will mark Intel's first gate-all-around (GAA) design and the company's first new transistor design since FinFET debuted in 2011. Intel's design features four stacked nanosheets, each surrounded entirely by a gate. Intel claims this design enables faster transistor switching while using the same drive current as multiple fins, but in a smaller area. This certainly seems plausible; Intel's competitors have also adopted GAA designs.

Intel isn't sharing much information about RibbonFET yet, but it bears a striking resemblance to IBM's recently announced GAA/nanosheet tech that it fabbed on a 2nm test wafer (images below). This is incredibly relevant, as Intel recently announced in its IDM 2.0 announcement that it would collaborate with IBM on future logic and packaging technologies. This partnership is important for Intel as it looks to recover from years of stagnation with its process technologies. During our briefings with IBM about its research results, the company was quite clear that its new 2nm tech will benefit all of its partners, including Intel. You can read more about IBM's similar tech here.

As we noted in our coverage of IBM's nanosheet/GAA tech, the smallest transistors in the world are of no use if you can't wire them together, and that has been one of the most pressing constraints to shrinking to smaller nodes.

Intel's new PowerVia technology seems to be a promising approach to navigating the problem with interconnects. PowerVia routes all power for the transistors directly to the transistors through the backside of the transistor. This essentially partitions power delivery to the backside of the transistors while data transmission interconnects remain in their traditional location on the other side.

Intel says that separating the power circuitry and the data-carrying interconnects improves voltage droop characteristics, allowing for faster transistor switching while enabling denser signal routing on the top of the chip. Signaling also benefits because the simplified routing enables the use of faster wires with reduced resistance and capacitance.

This technique will obviously pose many of its own challenges, such as the power delivery circuitry potentially serving as an insulating layer that traps heat within the transistors. It will be interesting to see how Intel tackles those potential pitfalls.

Intel 18A and High NA EUV

Intel didn't include it in the roadmap, but it already has its next-gen angstrom-class process in development. 'Intel 18A' is already planned for "early 2025" with enhancements to the RibbonFET transistors.

Intel's 18A will be the inflection point for using High NA EUV, which is a new ultra-precise version of EUV machines that can etch designs at smaller (<8nm) resolutions than current machines. These machines will be required to do single-patterning EUV at such fine geometries, while existing EUV tools would require less-desirable multi-patterning EUV techniques.

Intel says it will be the first company to receive a High NA EUV machine from ASML, signaling that it plans to lead with the next-gen EUV machines as opposed to lagging behind TSMC as it did with 10nm. It's noteworthy that while Intel did state that it would be first to receive a High NA EUV machine, it didn't claim that it would be the first to enter high volume manufacturing with High NA EUV.

Intel tells us that it will offer the leading-edge Intel 3 and the following nodes, including 20A and 18A, to its foundry customers. That means we will likely see Intel stick with offering its prospective foundry customers trailing edge nodes for now — Intel 3 doesn't enter production until the second half of 2023.

Intel's summary says that the company will achieve process performance parity with the industry leader, TSMC, in 2024, and take the lead in 2025. However, Intel's footnote specifies that this is based on performance-per-watt, and not transistor performance or density.

It's noteworthy this parity statement only applies to Intel's process tech, and not its end products. The company still plans to still compete with "leadership products" from now until 2025 through a combination of new microarchitectures, packaging innovations that tie together various technologies in new and more efficient ways (more on that below), and also by outsourcing some of its highest-end chip designs for the first time in its history. Intel says it will release both consumer and data center "CPU leadership" chips with an as-yet unspecified TSMC node in 2023.

Intel Packaging Update

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Intel's packaging update was a bit more spartan. The company announced that it would use EMIB packaging tech, which uses an embedded silicon bridge in a package to connect multiple dies, for its Sapphire Rapids processors, marking the first data center product with the interconnect technology. This has been a bit of an open secret, as pictures of Sapphire Rapids have already surfaced. However, Intel did reveal that it will improve next-gen EMIB from a 55-micron bump pitch to 45 microns.

Intel's Foveros 3D chip stacking technology debuted in the company's Lakefield processors that the company recently retired, but the next-gen Foveros implementation debuts in Intel's upcoming Meteor Lake processors. This generation of Foveros improves to a 36-micron bump pitch. 

Intel's upcoming Foveros Omni takes things a step further. This interconnect technology uses copper columns at the peripheries of the interconnected dies to deliver power, while TSV connections throughout the center of the die shuffle data between the chips. This differs from the first-gen Foveros because it separates the data and power transmission, allowing for cleaner routing for both power and data signals. In turn, this enables a tighter 25-micron bump pitch and allows mixing and matching different base dies. This technology is essentially the same as Intel's ODI packaging tech, which you can read more about here. 

Intel has also given its hybrid bonding tech a new use in conjunction with its Foveros packaging. Foveros Direct leverages die-on-wafer hybrid bonding (copper-to-copper) as an alternative to standard thermo-compression bonding. This new technique features aggressive sub-10nm bump pitches that increase interconnect density, simplify interconnect circuitry, and lower resistance and power consumption — all while serving up higher bandwidth. Intel has already taped out a stacked SRAM chip with hybrid bonding, and now the company is applying the technique to its Foveros interconnect. However, Intel hasn't stated when this tech will come to market.

Intel Renames Process Nodes — Continued

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Intel's decision to rename its process nodes will certainly garner plenty of criticism, but it is a necessary evil. Intel's process node naming was simple enough back in 1997, when node naming was based on the transistor's gate length (or M1 half-pitch metric), but the correlation between the physical measurement and the actual name of the node changed over time. In fact, the arrival of FinFET transistors killed the correlation between the two entirely. Now Intel's node naming changes come with either new technology or increased transistor density.

When it comes to nanometers, everyone knows that a smaller number is better for semiconductors. But while Intel's naming diverged from a physical measurement slowly, third-party foundries like TSMC and Samsung made more radical adjustments based on even simple changes to the underlying technology. That spurred name changes for situations like the move from planar to FinFET transistors, even when the transition didn't improve transistor density. Even PDK/BKM (Product Design Kit/Best Known Method) changes are enough of an excuse for third-party fabs to assign a new number to a process, turning the naming convention into more of a marketing exercise than a metric tied to any sort of physical measurement.

And the third-party foundries are winning the marketing wars. However, in the real world, a plethora of factors influence the economics and performance of a process node, such as transistor density, peak performance, performance per watt, different types of logic/circuits, SRAM density, and so on.

Intel's missteps with its 10nm node, which caused a string of '+' revisions and the delay of three following nodes, exacerbated the node naming issue as Intel ceded its process leadership to TSMC. Now, depending on when TSMC first ships its 3nm process, the company leads Intel by either one or two process nodes. That's particularly painful for Intel because while its process tech does lag TSMC, its naming lags, too, falsely amplifying the extent of TSMC's lead. Currently, based on transistor density, Intel's 10nm is more analogous to TSMC's 7nm, and Intel's 7nm is comparable to TSMC's 5nm, so a naming adjustment makes sense. 

Intel also shared some supporting quotes (in the album above) that point to others in the industry pointing out that node naming no longer has any correlation to the actual tech. (One of Intel's supporting quotes in the slide above says Intel 7nm is close to TSMC 3nm, but take that with a grain of salt.)

It makes sense for Intel to move forward to new naming now that it will compete more directly with TSMC and Samsung in the foundry market, but we're surprised that it chose to make the move at its 10nm generation instead of waiting for 7nm (which is now called Intel 4). Given that Intel has already shifted from its '+' naming to using full names, like 'Enhanced SuperFin,' the new naming adds yet another layer of confusion to interpreting the company's progress because it is applied to products that are already in flight. Let's hope Intel sticks to this naming convention, and its roadmap, at least for a while.

Paul Alcorn is the Deputy Managing Editor for Tom's Hardware US. He writes news and reviews on CPUs, storage and enterprise hardware.

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10 nm process

For the length in general and comparison, see 10 nanometres.

MOSFET technology node

This article needs attention from an expert in Electronics or Technology. The specific problem is: 10 nm/7 nm articles deviate from International Technology Roadmap for Semiconductors definitions, as marketing terms from TSMC and Samsung are used. In short, 7 nm Samsung/TSMC is equivalent to 10 nm Intel. Thus treating 10 nm Intel and 7 nm Samsung/TSMC at different articles due to marketing material not real measurements seems to be incorrect, specially when the pages refer to ITRS roadmap (duplicate note at other affected article). See the talk page for details. WikiProject Electronics or WikiProject Technology may be able to help recruit an expert.(April 2019)

In semiconductor fabrication, the International Technology Roadmap for Semiconductors (ITRS) defines the 10 nm process as the MOSFETtechnology node following the 14 nm node. "10 nm class" denotes chips made using process technologies between 10 and 20 nm.

All production "10 nm" processes are based on FinFET (fin field-effect transistor) technology, a type of multi-gate MOSFET technology that is a non-planar evolution of planar siliconCMOS technology. Samsung first started their production of 10 nm-class chips in 2013 for their multi-level cell (MLC) flash memory chips, followed by their SoCs using their 10 nm process in 2016. TSMC began commercial production of 10 nm chips in 2016, and Intel later began production of 10 nm chips in 2018.

Since 2009, however, "node" has become a commercial name for marketing purposes[1] that indicates new generations of process technologies, without any relation to gate length, metal pitch or gate pitch.[2][3][4] For example, GlobalFoundries' 7 nm processes are similar to Intel's 10 nm process, thus the conventional notion of a process node has become blurred.[5] TSMC and Samsung's 10 nm processes are somewhere between Intel's 14 nm and 10 nm processes in transistor density. The transistor density (number of transistors per square millimetre) is more important than transistor size, since smaller transistors no longer necessarily mean improved performance, or an increase in the number of transistors.


Egyptian-American engineer Mohamed Atalla and Korean-American engineer Dawon Kahng (the original inventors of the MOSFET in 1959)[6] in 1962 demonstrated a device that has a metallic layer with nanometric thickness sandwiched between two semiconducting layers, with the metal forming the base and the semiconductors forming the emitter and collector. They deposited metal layers (the base) on top of single crystalsemiconductor substrates (the collector), with the emitter being a crystalline semiconductor piece with a top or a blunt corner pressed against the metallic layer (the point contact). With the low resistance and short transit times in the thin metallic nanolayer base, the devices were capable of high operation frequency compared to bipolar transistors. The device demonstrated by Atalla and Kahng deposited gold (Au) thin films with a thickness of 10 nm on n-typegermanium (n-Ge) and the point contact was n-type silicon (n-Si).[7]

In 1987, Iranian-American engineer Bijan Davari led an IBM research team that demonstrated the first MOSFET with a 10 nm gate oxide thickness, using tungsten-gate technology.[8]

In 2002, an international team of researchers at UC Berkeley, including Shibly Ahmed (Bangladeshi), Scott Bell, Cyrus Tabery (Iranian), Jeffrey Bokor, David Kyser, Chenming Hu (Taiwan Semiconductor Manufacturing Company), and Tsu-Jae King Liu, demonstrated the first FinFET with 10 nm gate length.[9][10]

The ITRS's original naming of this technology node was "11 nm". According to the 2007 edition of the roadmap, by the year 2022, the half-pitch (i.e., half the distance between identical features in an array) for a DRAM should be 11 nm.

In 2008, Pat Gelsinger, at the time serving as Intel's Chief Technology Officer, said that Intel saw a 'clear way' towards the 10 nm node.[11][12]

In 2011, Samsung announced plans to introduce the 10 nm process the following year.[13] In 2012, Samsung announced eMMCflash memory chips that are produced using the 10 nm process.[14]

In actuality, "10 nm" as it is generally understood in 2018 is only in high-volume production at Samsung. GlobalFoundries has skipped 10 nm, Intel has not yet started high-volume 10 nm production, due to yield issues, and TSMC has considered 10 nm to be a short-lived node,[15] mainly dedicated to processors for Apple during 2017–2018, moving on to 7 nm in 2018.

There is also a distinction to be made between 10 nm as marketed by foundries and 10 nm as marketed by DRAM companies.

Technology production history[edit]

In April 2013, Samsung announced that it had begun mass production of multi-level cell (MLC) flash memory chips using a 10 nm-class process, which, according to Tom's Hardware, Samsung defined as "a process technology node somewhere between 10-nm and 20-nm".[16] On 17 October 2016, Samsung Electronics announced mass production of SoC chips at 10 nm.[17] The technology's main announced challenge has been triple patterning for its metal layer.[18][19]

TSMC began commercial production of 10 nm chips in early 2016, before moving onto mass production in early 2017.[20]

On 21 April 2017, Samsung started shipping their Galaxy S8 smartphone which uses the company's version of the 10 nm processor.[21] On 12 June 2017, Apple delivered second-generation iPad Pro tablets powered with TSMC-produced Apple A10X chips using the 10 nm FinFET process.[22]

On September 12, 2017, Apple announced the Apple A11, a 64-bit ARM-based system on a chip, manufactured by TSMC using a 10 nm FinFET process and containing 4.3 billion transistors on a die of 87.66 mm2.

In April 2018, Intel announced a delay in volume production of 10 nm mainstream CPUs until sometime in 2019.[23] In July the exact time was further pinned down to the holiday season.[24] In the meantime, however, they did release a low-power 10 nm mobile chip, albeit exclusive to Chinese markets and with much of the chip disabled.[25]

In June 2018 at VLSI 2018, Samsung announced their 11LPP and 8LPP processes. 11LPP is a hybrid based on Samsung 14 nm and 10 nm technology. 11LPP is based on their 10 nm BEOL, not their 20 nm BEOL like their 14LPP. 8LPP is based on their 10LPP process.[26][27]

Nvidia released their GeForce 30 series GPUs in September 2020. They are made on a custom version of Samsung's 8 nm process, called Samsung 8N, with a transistor density of 44.56 million transistors per mm².[28][29]

10 nm process nodes[edit]


ITRS Logic Device
Ground Rules (2015)
Samsung TSMC Intel (not real 10 nm node, see 7nm)
Process name 16/14 nm 11/10 nm 10 nm 11 nm 8 nm 10 nm 10 nm[a](comparable with 7 nm)
Transistor density (MTr / mm²) Un­known Un­known 51.82[27]54.38[27]61.18[27]52.51[31]100.8[32][b]
Transistor gate pitch (nm) 70 48 68 ? 64 66 54
Interconnect pitch (nm) 56 36 51 ? ? 44 36
Transistor fin pitch (nm) 42 36 42 ? 42 36 34
Transistor fin height (nm) 42 42 49 ? ? Un­known 53
Production year 2015 2017 2017[27]2018 2018 2016[c]
  1. ^Measurements of the process used for Cannon Lake in 2018. It is unclear whether these will be the same for Intel's next 10nm process in 2019.[30]
  2. ^Intel uses this formula:[33]{\displaystyle {\rm {No.\ Transistors/mm^{2}=0.6\cdot {\frac {\rm {NAND2\ Tr\ Count}}{\rm {NAND2\ Cell\ Area}}}+0.4\cdot {\frac {\rm {Scan\ Flip\ Flop\ Tr\ Count}}{\rm {Scan\ Flip\ Flop\ Cell\ Area}}}}}}
  3. ^accepting tape-outs[20]
  4. ^high volume shipment[20]

Transistor gate pitch is also referred to as CPP (contacted poly pitch) and interconnect pitch is also referred to as MMP (minimum metal pitch). Samsung reported their 10 nm process as having a 64 nm transistor gate pitch and 48 nm interconnect pitch. TSMC reported their 10 nm process as having a 64 nm transistor gate pitch and 42 nm interconnect pitch. Further investigation by Tech Insights revealed these values to be false and they have been updated accordingly. In addition, the transistor fin height of Samsung's 10 nm process was updated by MSSCORPS CO at SEMICON Taiwan 2017.[34][35][36][37][38] GlobalFoundries decided not to develop a 10 nm node, because it believed it would be short lived.[39] Samsung's 8 nm process is the company's last to exclusively use DUV lithography.[40]

DRAM "10 nm class"[edit]

Main article: Dynamic random-access memory

For the DRAM industry, the term "10 nm-class" is often used and this dimension generally refers to the half-pitch of the active area.[citation needed] The "10 nm" foundry structures are generally much larger.[citation needed]

Generally 10 nm class refers to DRAM with a 10-19 nm feature size, and was first introduced c. 2016. As of 2020 there are three generations of 10 nm class DRAM : 1x nm (19-17 nm, Gen1); 1y nm (16-14 nm, Gen2); and 1z nm (13-11 nm, Gen3).[41] 3rd Generation "1z" DRAM was first introduced c.2019 by Samsung, and was initially stated to be produced using ArF lithography without the use of EUV lithography;[42][43] subsequent production did utilise EUV lithography.[44]

Beyond 1z Samsung names its next node (fourth generation 10 nm class) DRAM : "D1a" (for 2021), and beyond that D1b (expected 2022); whilst Micron refers to succeeding "nodes" as "D1α" and "D1β".[45] Micron announced volume shipment of 1α class DRAM in early 2021.[46]


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  2. ^Shukla, Priyank. "A Brief History of Process Node Evolution". Retrieved 2019-07-09.
  3. ^Hruska, Joel. "14nm, 7nm, 5nm: How low can CMOS go? It depends if you ask the engineers or the economists…". ExtremeTech.
  4. ^"Exclusive: Is Intel Really Starting To Lose Its Process Lead? 7nm Node Slated For Release in 2022". 2016-09-10.
  5. ^"Life at 10nm. (Or is it 7nm?) And 3nm - Views on Advanced Silicon Platforms". 2018-03-12.
  6. ^"1960: Metal Oxide Semiconductor (MOS) Transistor Demonstrated". The Silicon Engine. Computer History Museum. Retrieved August 31, 2019.
  7. ^Pasa, André Avelino (2010). "Chapter 13: Metal Nanolayer-Base Transistor". Handbook of Nanophysics: Nanoelectronics and Nanophotonics. CRC Press. pp. 13–1, 13–4. ISBN .
  8. ^Davari, Bijan; Ting, Chung-Yu; Ahn, Kie Y.; Basavaiah, S.; Hu, Chao-Kun; Taur, Yuan; Wordeman, Matthew R.; Aboelfotoh, O.; Krusin-Elbaum, L.; Joshi, Rajiv V.; Polcari, Michael R. (1987). "Submicron Tungsten Gate MOSFET with 10 nm Gate Oxide". 1987 Symposium on VLSI Technology. Digest of Technical Papers: 61–62.
  9. ^Tsu‐Jae King, Liu (June 11, 2012). "FinFET: History, Fundamentals and Future". University of California, Berkeley. Symposium on VLSI Technology Short Course. Retrieved 9 July 2019.
  10. ^Ahmed, Shibly; Bell, Scott; Tabery, Cyrus; Bokor, Jeffrey; Kyser, David; Hu, Chenming; Liu, Tsu-Jae King; Yu, Bin; Chang, Leland (December 2002). "FinFET scaling to 10 nm gate length"(PDF). Digest. International Electron Devices Meeting: 251–254. CiteSeerX doi:10.1109/IEDM.2002.1175825. ISBN . S2CID 7106946. Archived from the original(PDF) on 2020-05-27. Retrieved 2019-10-12.
  11. ^Damon Poeter (July 2008). "Intel's Gelsinger Sees Clear Path To 10nm Chips". Archived from the original on 2009-06-22. Retrieved 2009-06-20.
  12. ^"MIT: Optical lithography good to 12 nanometers". Archived from the original on 2009-06-22. Retrieved 2009-06-20.
  13. ^"World's Largest Fabrication Facility, Line-16". Samsung. September 26, 2011. Retrieved 21 June 2019.
  14. ^"Samsung's new 10nm-process 64GB mobile flash memory chips are smaller, faster, better". Engadget. November 15, 2012. Retrieved 21 June 2019.
  15. ^"10nm rollout". Archived from the original on 2018-08-04. Retrieved 2018-08-04.
  16. ^"Samsung Mass Producing 128Gb 3-bit MLC NAND Flash". Tom's Hardware. 11 April 2013. Archived from the original on 21 June 2019. Retrieved 21 June 2019.
  17. ^Samsung Starts Industry's First Mass Production of System-on-Chip with 10-Nanometer FinFET Technology, Oct 2016
  18. ^"Samsung Starts Industry's First Mass Production of System-on-Chip with 10-Nanometer FinFET Technology".
  19. ^"triple patterning for 10nm metal"(PDF).
  20. ^ abc"10nm Technology". TSMC. Retrieved 30 June 2019.
  21. ^"Buy".
  22. ^ "10nm Rollout Marching Right Along". Archived from the original on 2017-08-03. Retrieved 2017-06-30.
  23. ^"Intel Corp. Delays 10nm Chip Production - Mass production is now scheduled for 2019". 2018-04-29. Retrieved 2018-08-01.
  24. ^"Intel says not to expect mainstream 10nm chips until 2H19". 2018-07-28. Retrieved 2018-08-01.
  25. ^"Intel's First 10nm Processor Lands In China". 2018-05-15. Retrieved 2018-09-11.
  26. ^"VLSI 2018: Samsung's 11nm nodelet, 11LPP". WikiChip Fuse. 2018-06-30. Retrieved 2019-05-31.
  27. ^ abcde"VLSI 2018: Samsung's 8nm 8LPP, a 10nm extension". WikiChip Fuse. 2018-07-01. Retrieved 2019-05-31.
  28. ^"Nvidia confirms Samsung 8nm process for RTX 3090, RTX 3080, and RTX 3070 | PC Gamer".
  29. ^"NVIDIA GeForce RTX 30 Ampere GPU Deep-Dive, Full Specs, Thermals, Power & Performance Detailed". September 4, 2020.
  30. ^Demerjian, Charlie (2018-08-02). "Intel guts 10nm to get it out the door". SemiAccurate. Retrieved 29 September 2018.
  31. ^Schor, David (2019-04-16). "TSMC Announces 6-Nanometer Process". WikiChip Fuse. Retrieved 2019-05-31.
  32. ^"Intel 10nm density is 2.7X improved over its 14nm node". HEXUS. Retrieved 2018-11-14.
  33. ^Bohr, Mark (2017-03-28). "Let's Clear Up the Node Naming Mess". Intel Newsroom. Retrieved 2018-12-06.
  34. ^"Intel Details Cannonlake's Advanced 10nm FinFET Node, Claims Full Generation Lead Over Rivals". 2017-03-28. Archived from the original on 2017-03-30. Retrieved 2017-03-30.
  35. ^"International Technology Roadmap for Semiconductors 2.0 2015 Edition Executive Report"(PDF). Retrieved 2018-12-27.
  36. ^Jones, Scotten. "14nm 16nm 10nm and 7nm - What we know now".
  37. ^"Qualcomm Snapdragon 835 First to 10 nm".
  38. ^"10 nm lithography process". wikichip.
  39. ^Jones, Scotten. "Exclusive - GLOBALFOUNDRIES discloses 7nm process detail".
  40. ^Shilov, Anton. "Samsung's 8LPP Process Technology Qualified, Ready for Production".
  41. ^Mellor, Chris (13 April 2020), "Why DRAM is stuck in a 10nm trap",
  42. ^Shilov, Anton (21 March 2019), "Samsung Develops Smaller DDR4 Dies Using 3rd Gen 10nm-Class Process Tech",
  43. ^Samsung Develops Industry's First 3rd-generation 10nm-Class DRAM for Premium Memory Applications (press release), Samsung, 25 Mar 2019
  44. ^Samsung Announces Industry's First EUV DRAM with Shipment of First Million Modules (press release), Samsung, 25 Mar 2020
  45. ^Choe, Jeongdong (18 Feb 2021), "Teardown: Samsung's D1z DRAM with EUV Lithography",
  46. ^Micron Delivers Industry's First 1α DRAM Technology (press release), Micron, 26 Jan 2021

Intel May Change Its Process Node Numbering to Align With TSMC, Samsung


Intel is reportedly considering changing its process node numbering system in a bid to look better against Samsung and TSMC. As solutions to Intel’s problems go, renumbering its process nodes isn’t going to close technical gaps between itself and TSMC. If Intel is serious about entering the client foundry business, however, it may need to patch up its marketing.

Ann Kelleher, the Hillsboro VP in charge of Intel’s manufacturing group, has notified employees that “Intel plans to change its numbering conventions to match the industry standard,” according to Oregon Live. The phrase “industry standard” is doing a lot of heavy lifting here because there is no ‘industry standard.’ As we’ve discussed in the past, process nodes are arbitrary designations intended to convey a sense of progress. TSMC’s 7nm technology is different than Intel’s still-unlaunched 7nm, which is different from Samsung’s 7nm.

The chart above shows a comparison between 10nm technologies for Intel, TSMC, and Samsung. Intel’s contacted gate pitch and minimum metal pitch are both much lower than what TSMC and Samsung defined for their own 10nm or even 7nm, in a few specific metrics. When Intel claims that its 10nm technology looks more like TSMC and Samsung’s 7nm technology, it’s telling the truth. If Intel changes its node naming to more closely reflect what TSMC and Samsung are doing, it will arguably improve a customer’s ability to understand comparisons between the different foundries.

The significance of this proposed transition is that Intel is making it in the first place. Intel defined the names for various nodes in the past because it was always the company moving to those nodes first. TSMC sometimes offered its own half-node options and it hasn’t always moved in lockstep with Intel, but it’s now leading the entire semiconductor industry. It makes more sense for Intel to rebrand its arbitrary numbers to align with what its competitors are doing.

But make no mistake: Intel might figuratively grit its teeth about changing its naming scheme, but the current system genuinely leaves people with the wrong idea. I don’t know what Intel would adopt, but if the company goes through with this, you may see some frustration over Intel supposedly ‘cheating’ to hit whatever number they alternately use. It won’t be true.

Intel may be changing its branding to align with its own plans to build Core CPUs outside of Intel itself. If Intel launches a chip built at TSMC on 5nm and its own CPUs are still shipping on 10nm, that’s going to look odd. It’ll look especially odd if Intel plans to jointly manufacture its own hardware simultaneously. Whenever a company dual sources, there’s a bit of a dance to make certain all of the versions of the product from all of the different manufacturers perform similarly. We don’t have the details of exactly what Intel is planning for the future, but it’s possible the company doesn’t want to try and explain how two different chips can be built on two different process nodes while simultaneously extolling the benefits of its own manufacturing.

Now Read:


Node intel process

This article details Intel's semiconductor process technology history for research and posterity.


The table below shows the history of Intel's process scaling. Values were taken from various Intel documents including IDF presentations, ISSCC papers, and IEDM papers. Note that while a great deal of effort was put into ensuring the accuracy of the values, some numbers vary to a small degree between Intel's own documents and therefore discrepancies may exist. SRAM bitcell areas refer to a high-density 6T bitcell with the exception of the very first few processes where smaller cell designs were used. Additionally, the metal layer count is for the client dies (example consumer mobile & desktop); server models utilize considerably more layers. Finally, from the 45 nm node, Intel has switched to utilizing a high-κ material, therefore the oxide thickness shown refers to the equivalent oxide thickness instead.


Intel has been using the same naming scheme for decades. All process technologies (including packaging technologies) begin with a 'P' followed by the wafer size and the process ID. Generally, the process ID is an auto-increment value with odd values generally reserved for SoC and I/O (low power) devices while the even values have been used for Intel premier line of high-performance processors.

intel process naming scheme.svg


Intel's fab roadmap from 2003. Intel had to switch to FinFET after gate length scaling stalled due to subpar electrical characteristics.
Intel roadmap from 10 nmto 5 nmand an advance packaging roadmap.

SRAM Scaling[edit]

For Intel, from 2 µm to 10 nm, SRAM 6T bit cells have had an average shrink of 0.496x in an attempt to maintain Moore's Law double density observation/requirement. Note that SRAM shrunk more significantly prior to the 65 nm process node. It should also be noted that logic typically scales better than the typical 6T SRAM cells, so raw logic density scaled more over time. Nonetheless, the size of the SRAM can be as much as three to four times the density of the typical logic cell.

intel sram bit cell scaling.png

Other processes[edit]

Semiconductor Process history by company:

See also[edit]

Intel Performance Leadership in 2025: Beyond Nanometers

Intel Announces Process Roadmap Through 2025 & Beyond: New Naming Scheme, 10nm ESF Now Intel 7, 7nm Now Intel 4, Intel 3, Intel 20A & Beyond

During its IDM 2.0 keynote, Intel's CEO, Pat Gelsinger, unveiled his company's brand new process roadmap along with a refreshing new naming scheme for next-generation nodes. The brand new roadmap covers all nodes and the respective products that we can expect to enter manufacturing and production through 2025 and beyond.

Intel Process Roadmap & Innovation Roadmap Highlights Brand New Node Naming Scheme, Drops '++' & 'SuperFin' Brandings

Intel is restructuring as a whole under its new leadership and it looks like the process nodes, that have been confusing over the past few years, will finally be understandable for the general public. Intel recently has its 10nm SuperFin process node which is an enhanced variant of the Intel 10nm (++) node utilized by Ice Lake chips. Currently, Intel has both 10nm and 14nm chips within mobile and desktop platforms but that's going to change later this year when Intel finally brings forth its Alder Lake and Sapphire Rapids lineup.

Corsair’s Next-Gen AIO Liquid Coolers Leaked Soon After Tease, Ready For Intel Alder Lake Desktop CPUs

Under IDM 2.0, our factory network continues to deliver and we are now manufacturing more 10-nanometer wafers than 14-nanometer. As 10-nanometer volumes ramp, economics are improving with 10-nanometer wafer cost 45% lower year-over-year with more to come.

via Intel

Intel 7 Process Node (Previously 10nm Enhanced SuperFin)

So first up, we have Intel 7, a new name for the company's 10nm Enhanced SuperFin process node. This node was going to power Intel's Alder Lake Client and Sapphire Rapids Server lineup. Based on what Intel has stated, the node will offer a 10-15% performance per watt gain over 10nm SuperFin and feature FinFET transistor optimizations. Intel 7 is ready for volume production and the first products are expected to land on market by Q4 2021

Intel 7 delivers an approximately 10% to 15% performance-per-watt increase versus Intel 10nm SuperFin, based on FinFET transistor optimizations. Intel 7 will be featured in products such as Alder Lake for client in 2021 and Sapphire Rapids for the data center, which is expected to be in production in the first quarter of 2022.

  • 2021-07-27_2-27-20
  • 2021-07-27_2-27-28

Intel 4 Process Node (Previously 7nm)

Intel 4 is also something that the company has previously referred to as its 7nm process node. This is a much hyped-up node as it powers several next-generation products including Ponte Vecchio & along with that, we have Meteor Lake for Client and Granite Rapids for datacenters. Intel is claiming a 20% performance per watt gain for Intel 4 over Intel 7. In addition to these, Intel 4 will deliver a good list of enhancements over 10nm which will include:

More Intel Core i9-12900K Alder CPU Synthetic & Gaming Benchmarks Leak Out

  • 2x density scaling vs Intel 7
  • Planned intra-node optimizations
  • 4x reduction in design rules
  • EUV
  • Next-Gen Foveros & EMIB Packaging

The node will also make full use of EUV Lithography and already has products taping out such as the Meteor Lake Compute Tile which was taped out during the previous quarter. Granite Rapids will also feature a multi-compute tile design and its main Granite Rapids core will be fabricated on the Intel 4 node.

Intel 4 fully embraces EUV lithography to print incredibly small features using ultra-short wavelength light. With an approximately 20% performance-per-watt increase, along with area improvements, Intel 4 will be ready for production in the second half of 2022 for products shipping in 2023, including Meteor Lake for client and Granite Rapids for the data center.

Intel 3 Process Node (An Intel 4 Optimization?)

Moving beyond Intel 4, the company plans to launch its Intel 3 process node which would be ready for manufacturing products by the second half of 2023. Based on everything that Intel has listed, it looks like Intel 3 is a generational optimization of Intel 4 as it delivers an 18% performance per watt gain, offers denser HP libraries, increases the intrinsic driver current, increased EUV use & reduces via resistance.

It looks like everything beyond Meteor Lake (Lunar Lake) and Granite Ridge (Diamond Rapids) could utilize the Intel 3 process node though we are talking about products that would launch in 2024 or even 2025 by the earliest so there's a long way to go.

Intel 3 leverages further FinFET optimizations and increased EUV to deliver an approximately 18% performance-per-watt increase over Intel 4, along with additional area improvements. Intel 3 will be ready to begin manufacturing products in the second half of 2023.

Intel 20A Process Node & Beyond (A True Next-Gen Node)

Intel has gone ahead to talk about its post-nanometer era with a new product it is referring to as Intel 20A. The Intel 20A starts the Angstrom era (A for Angstrom) which is equal to 10⁻¹⁰ m or 1A = 0.1nm. This is just a cool way of saying 2nm but given how small nodes have gotten and the fact that we are heading down to decimal spaces within this decade, Intel decided a new measuring unit was needed.

  • 2021-07-27_2-28-00
  • 2021-07-27_2-28-08

So Intel 20A (2nm) is going to offer breakthrough innovations when it enters the early production phase by 1H 2024. The 20A node is expected to feature brand new RibbonFET transistors that will replace the existing FinFET architecture and also deliver new interconnect innovations, one of which is known as PowerVia. Intel is also expanding upon its Forveros technologies with Omni and Direct. Forveors Omni will be featured in products that package high-performance compute tiles while Forveors Direct will allow multi-tier interconnector resistance through a copper to copper bond. Forveros as a whole will be updated to deliver increased bandwidth through next-gen inter-connect solutions.

Intel 20A ushers in the angstrom era with two breakthrough technologies, RibbonFET and PowerVia. RibbonFET, Intel’s implementation of a gate-all-around transistor, will be the company’s first new transistor architecture since it pioneered FinFET in 2011. The technology delivers faster transistor switching speeds while achieving the same drive current as multiple fins in a smaller footprint. PowerVia is Intel’s unique industry-first implementation of backside power delivery, optimizing signal transmission by eliminating the need for power routing on the front side of the wafer. Intel 20A is expected to ramp in 2024.

  • Foveros Omni ushers in the next generation of Foveros technology by providing unbounded flexibility with performance 3D stacking technology for die-to-die interconnect and modular designs. Foveros Omni allows die disaggregation, mixing multiple top die tiles with multiple base tiles across mixed fab nodes and is expected to be ready for volume manufacturing in 2023.
  • Foveros Direct moves to direct copper-to-copper bonding for low-resistance interconnects and blurs the boundary between where the wafer ends and where the package begins. Foveros Direct enables sub-10 micron bump pitches providing an order of magnitude increase in the interconnect density for 3D stacking, opening new concepts for functional die partitioning that were previously unachievable. Foveros Direct is complementary to Foveros Omni and is also expected to be ready in 2023.

Intel Process Roadmap

Process NameIntel 10nm SuperFinIntel 7Intel 4Intel 3Intel 20AIntel 18A
ProductionIn High-Volume (Now)In Volume (Now)2H 20222H 20232H 20242H 2025
Perf/Watt (over 10nm ESF)N/A10-15%20%18%>20%?TBA
Transistor ArchitectureFinFETOptimized FinFETOptimized FinFETOptimized FinFETRibbonFETOptimized RibbonFET
ProductsTiger LakeAlder Lake
Sapphire Rapids
Meteor Lake
Granite Rapids
Xe-HPC / Xe-HP?
Lunar Lake?
Diamond Rapids?

As for products based on the Intel 20A process node, don't expect them to be a reality prior to 2025. Also, based upon the older roadmaps and where 20A is positioned, it looks to be either a rename of Intel's 5nm or 3nm process node. but more scaled up to add in the '+' optimizations which have been excluded from now onwards.

Intel doesn't stop at 20A though, they go on to discuss next-generation nodes through 2025 and beyond which would include 18A. The 18A node is already in development for early 2025 and will feature refinements to the RibbonFET architecture to deliver another major leap in transistor and chip performance.

Intel's Process and Manufacturing Roadmap for the next 10 years shows 10nm, 7nm, 5nm, 3nm, 2nm and 1.4nm. (Image Credits: Anandtech)

Intel's Process and Manufacturing Roadmap for the next 10 years shows 10nm, 7nm, 5nm, 3nm, 2nm, and 1.4nm. (Image Credits: Anandtech)

These new innovations and naming schemes are great to avoid the mess that Intel was headed into just a few years back. The company had process node roadmaps lineup with several nodes & their respective backports + optimizations in a really confusing manner. Now, Intel can move forward without worrying about the naming schemes and offer a unified process node lineup under its new naming criteria.

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Intel's Process Roadmap to 2025: with 4nm, 3nm, 20A and 18A?!

In today’s Intel Accelerated event, the company is driving a stake into the ground regarding where it wants to be by 2025. CEO Pat Gelsinger earlier this year stated that Intel would be returning to product leadership in 2025, but hasn’t yet explained how this is coming about – that is until today, where Intel has disclosed its roadmap for its next five generations of process node technology leading to 2025. Intel believes it can follow an aggressive strategy to match and pass its foundry rivals, while at the same time developing new packaging offerings and starting a foundry business for external customers. On top of all this, Intel has renamed its process nodes.

The Short Answer:

If you only take one thing away from this article, I'm going to put it here front and center. Here is what we're seeing for Intel's roadmaps, based on their disclosures today.

As always, there is a difference between when a technology ramps for production and comes to retail; Intel spoke about some technologies as 'being ready', while others were 'ramping', so this timeline is simply those dates as mentioned. As you might imagine, each process node is likely to exist for several years, this graph is simply showcasing the leading technology from Intel at any given time.

If you want the details on this graph, then read on.

Intel's Defines a Strong Future: Is TSMC at Risk?

Earlier this year, CEO Pat Gelsinger announced Intel’s new IDM 2.0 strategy, consisting of three elements:

  1. Build (7nm)
  2. Expand (TSMC)
  3. Productize (Intel Foundry Services)

The goal here is to continue to work on Intel’s process node technology development, going beyond the current 10nm designs in production today, but simultaneously using other foundry services from partners (or competitors) to regain/retain Intel’s position in its processors that drive a lot of the company revenue. The third element is IFS, Intel’s Foundry Services, where Intel is committing in a big way to opening up its manufacturing facilities to external semiconductor business.

Underpinning (1) and (3) is how Intel executes on its own process node development. While in Intel’s recent Q3 2021 earnings call CEO Gelsinger confirmed that Intel is now producing more 10nm wafers in a day than 14nm wafers, marking a shift in confidence between the two designs, it is no secret that Intel has had difficulty in transitioning from its 14nm process to its 10nm process. On June 29th this year, Intel also stated that its next generation 10nm product requires additional validation time to streamline deployment on enterprise systems for 2022. Note that at the same time, TSMC has surpassed Intel by shipping at capacity with its equivalent designs (called 7nm) and its leading edge (5nm) designs that surpass Intel’s performance.

As with the previous announcement in March, Intel is reaffirming that it intends to return to leadership performance in semiconductors in 2025. This will enable both the company to compete better as it builds its own products (1) but also offer a wider portfolio of performance and technologies for its future IFS customers (3). To do this, it is realigning the roadmap for its future process node technologies to be more aggressive with improvements, yet at the same time more modular with its technology to enable faster transitions.

Leading up this plan is Dr. Ann B Kelleher, who was named SVP and GM of the Technology Development division at Intel last year. This division is where all the research and development of Intel’s future process node technologies and enhancements comes from – it used to be part of Intel’s System Architecture Group, however it was split in July 2020 to re-establish a focus purely on Technology Development. Dr. Kelleher’s background involves process research in academia, followed by 26 years at Intel as a process engineer, moving up to managing Fab 24 in Ireland, Fab 12 in Arizona, Fab 11X in Rio Rancho, before landing in HQ in Oregon as the GM of Manufacturing and Operations.

Her experience covering both fab-scale production and process node research is going to be critical for Intel’s future plans. In discussing with Kelleher ahead of today’s announcements, she stated that she has implemented fundamental changes when it comes to supplier approach, ecosystem learnings, organizational changes, modular design strategies, contingency plans, and realigning the Technology Development Team into a more streamlined outfit ready to execute. These include key personnel such as Sanjay Natarajan as SVP and GM of Logic Development (one of Intel’s recent rehires) and Babak Sabi as CVP and GM of Assembly/Test Development

Intel is today defining ‘technology leadership by 2025’ as defined by the metric of performance per watt. We asked Intel is a pre-briefing what that means for peak performance, which is often a metric we care about for end product design, and the answer was that "peak performance remains a key part of Intel’s strategic development".

Intel Renames The Nodes: ‘Mine is Smaller’

The problem with simply posting Intel’s roadmap here is that the news is two-fold. Not only is Intel disclosing the state of its technology for the next several years, but the names of the technology are changing to better align with common industry norms.

It is no secret that having "Intel 10nm" being equivalent to "TSMC 7nm", even though the numbers actually have nothing to do with the physical implementation, has ground at Intel for a while. A lot of the industry, for whatever reason, hasn’t learned that these numbers aren’t actually a physical measurement. They used to be, but when we moved from 2D planar transistors to 3D FinFET transistors, the numbers became nothing more than a marketing tool. Despite this, every time there’s an article about the technology, people get confused. We’ve been talking about it for half a decade, but the confusion still remains.

To that end, Intel is renaming its future process nodes. Here’s the roadmap image, but I’ll be breaking it down piece by piece.

2020, Intel 10nm SuperFin (10SF): Current generation technology in use with Tiger Lake and Intel’s Xe-LP discrete graphics solutions (SG1, DG1). The name stays the same.

2021 H2, Intel 7: Previously known as 10nm Enhanced Super Fin or 10ESF.  Alder Lake and Sapphire Rapids will now be known as Intel 7nm products, showcasing a 10-15% performance per watt gain over 10SF due to transistor optimizations. Alder Lake is currently in volume production. Intel’s Xe-HP will now be known as an Intel 7 product.

2022 H2, Intel 4: Previously known as Intel 7nm. Intel earlier this year stated that its Meteor Lake processor will use a compute tile based on this process node technology, and the silicon is now back in the lab being tested. Intel expects a 20% performance per watt gain over the previous generation, and the technology uses more EUV, mostly in the BEOL. Intel’s next Xeon Scalable product, Granite Rapids, will also use a compute tile based on Intel 4.

2023 H2, Intel 3: Previously known as Intel 7+. Increased use of EUV and new high density libraries. This is where Intel’s strategy becomes more modular – Intel 3 will share some features of Intel 4, but enough will be new enough to describe this a new full node, in particular new high performance libraries. Nonetheless, a fast follow on is expected. Another step up in EUV use, Intel expects a manufacturing ramp in the second half of 2023 with an 18% performance per watt gain over Intel 4.

2024, Intel 20A: Previously known as Intel 5nm. Moving to double digit naming, with the A standing for Ångström, or 10A is equal to 1nm. Few details, but this is where Intel will move from FinFETs to its version of Gate-All-Around (GAA) transistors called RibbonFETs. Also Intel will debut a new PowerVia technology, described below.

2025, Intel 18A: Not listed on the diagram above, but Intel is expecting to have an 18A process in 2025. 18A will be using ASML’s latest EUV machines, known as High-NA machines, which are capable of more accurate photolithography. Intel has stated to us that it is ASML’s lead partner when it comes to High-NA, and is set to receive the first production model of a High-NA machine. ASML recently announced High-NA was being delayed- when asked if this was an issue, Intel said no, as the timelines for High-NA and 18A are where Intel expects to intersect and have unquestioned leadership.

Intel has confirmed to us that Intel 3 and Intel 20A will be offered to foundry customers (but hasn’t stated if Intel 4 or Intel 7 will be).

To bring this altogether in a single table, with known products, we have the following:

Intel's Process Node Technology
Old NameNew NameRoadmapProductsFeatures
10SF10SFTodayTiger Lake
Xe-HPC Base Tile
Agilex-F/I FPGA
Thin Film Barrier
Volume 10nm
On sale today
10ESFIntel 72021 H2 productsAlder Lake (21)
Raptor Lake (22)?
Sapphire Rapids (22)
Xe-HPC IO Tile
10-15% PPW
Upgraded FinFET
ADL in Ramp today
7nmIntel 42022 H2 ramp
2023 H1 products
Meteor Compute Tile
Granite Compute Tile
20% PPW vs 7
More EUV
Silicon in Lab
7+Intel 32023 H2 products-18% PPW vs 4
Area Savings
More EUV
New Perf Libraries
Faster Follow On
5nmIntel 20A2024-RibbonFET
5+Intel 18A2025Unquestioned Leadership2nd Gen Ribbon

One of the issues here is the difference between a process node being ready, ramping production for product launches, and actually being made available. For example, Alder Lake (now on Intel 7nm) is due to come out this year, but Sapphire Rapids is going to be more of a 2022 product. Similarly, there are reports of Raptor Lake on Intel 7 coming out in 2022 to replace Alder Lake with the tiled Meteor Lake on Intel 4 in 2023. While Intel is happy to discuss process node development time frames, product timeframes are not as open (as no doubt customers would get frustrated if the time stated is missed).

Why The Nodes Were Renamed

So as stated before, one element of renaming the nodes is due to matching parity with other foundry offerings. Both TSMC and Samsung, competitors to Intel, were using smaller numbers to compare similar density processes. With Intel now renaming itself, it gets more in-line with the industry. That being said, perhaps sneakily, Intel’s 4nm might be on par with TSMC’s 5nm, reversing the tables. By 3nm we expect there to be a good parity point, however that will depend on Intel matching TSMC’s release schedule.

Rather than throw process node names everywhere, it is typical to refer to peak quoted transistor densities instead. Here is the table we published in our recent IBM 2nm news post, but with an updated shift on Intel’s naming.

2021 Peak Quoted Transistor Densities (MTr/mm2)
Process Name
22nm  16.50 
16nm/14nm 28.8844.6733.32
10nm 52.51100.7651.82
7nm 91.20100.7695.08
5/4nm 171.30~200*126.89
3nm 292.21*  
2nm / 20A333.33   
Data from Wikichip, Different Fabs may have different counting methodologies
* Estimated Logic Density

Exactly where Intel’s new 4nm and below will end up is yet to be disclosed, as numbers with stars alongside are based on estimates by the respective companies.

It has been expected for a while that Intel would be realigning its process node naming. Behind closed doors, I personally have been lobbying for it for a while, and I know that a few other journalists and analysts have been suggesting it to Intel as well. Some responses we received were related to apathy – one executive told me that "our customers that care about this actually know the difference", which is true for sure, but what we’re talking about here is more about perception in the wider ecosystem for enthusiasts and financial analysts who might not be up to speed. It is more or less a branding exercise, and I also told Intel that they are going to have to expect a mixed response – some voices might interpret the move as Intel trying to pull one over on the market, for example. But they’re going to have to live with it, as these are the new names.

Meanwhile, despite Intel’s struggles with 10nm, it is still a process node in production and in volume production, in use for both consumer and enterprise devices, and it's coming to desktops very soon. Even though it has some stiff competition from other players, it is still an offering in the market, and for those that want to compare process node densities using these names, it should have a moniker to avoid confusion. I am applauding that Intel is doing it sooner rather than later.

One key point to note is that the new Intel 7 node, which was formerly the 10ESF node, is not necessarily a "full" node update as we typically understand it. This node is derived as an update from 10SF, and as the diagram above states, will have ‘transistor optimizations’. Moving from 10nm to 10SF, that meant SuperMIM and new thin-film designs giving an extra 1 GHz+, however the exact details from 10SF to the new Intel 7 is unclear at this point. Intel has however stated that moving from Intel 7 to Intel 4 will be a regular full node jump, with Intel 3 using modular parts of Intel 4 with new high-performance libraries and silicon improvements for another jump in performance.

We asked Intel if these process nodes will have additional optimization points, and were told that they will – whether any of them will be explicitly productized will depend on the features. Individual optimizations may account for an additional 5-10% performance per watt, and we were told that even 10SF (which keeps its name) has had several additional optimization points that haven’t necessarily been publicized. So whether these updates get marketed as 7+ or 7SF or 4HP is not known, but as with any manufacturing process as updates occur to help improve performance/power/yield, they get applied assuming the design adheres to the same rules.

"Isn't Intel Just Trying To Pull The Wool Over Our Eyes?"


The problem here is that there is no consistent node naming between foundries. Intel has been saving any number change for major advances in its node manufacturing technology, instead using +/++ to signify improvements. If we compare this to TSMC and Samsung, both of whom have been happy to give half-node jumps new numbers entirely.

For example, Samsung's 7LPP is a major node, however 6LPP, 5LPE and 4LPE are all iterative efforts on the same design (arguably also iterative of 8LPP), with 3GAE being the next major jump. Compare this to Intel, who was planning 10nm to 7nm to 5nm as major process node jumps – so while Samsung had one jump planned and 4 sub-variants (or more), Intel had two major jumps. Similarly, TSMC's 10nm was a half-node jump over 16nm, while 16nm to 7nm was the full node – Intel made 14 to 10 to 7 as full nodes.

Intel stuck to its guns a long while, and delays to 10nm effectively hurt it in a multiplicative fashion. For example, if Intel had labeled 14+ as 13nm, and 14++ as 12nm, perhaps it wouldn't be so bad. I mean, yes Intel should expect some hurt for 10nm being late, but when other foundries were showcasing smaller steps as full number jumps, it became a marketing and media nightmare. 14++++ became an industry joke, and coupled with how every time when they talked about future process nodes they had to cite the equivalent TSMC of Samsung process, it got a bit too much. It had to be explained every time, as new people come into the industry.  

I've lobbied Intel to adjust its naming for a while, and I know other peers have as well. When we refer to Intel 7 from now on, we can draw equivalents to TSMC 7nm (even if TSMC is shipping 5nm in volume) without having to extensively explain differences in a simple name. This isn't Intel pulling the wool over your eyes, or trying to hide a bad situation. This is Intel catching up to the rest of the industry in how these processes are named. To add to this, it's a good thing that Intel is only renaming future nodes that haven't reached the market yet.

This is a multi-page article!

Click the dropdown below for more pages, including

  1. This Page, New Node Names
  2. A Sidebar on Intel EUV and becoming ASML Lead Partner
  3. New for 2024: RibbonFETs and PowerVias
  4. Next Gen EMIB and Foveros Packaging
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